Silicon films or features made by depositing cyclopentasilane or polycyclopentasilane are generally slightly n-type. This may be due to one or more factors that may include possible impurities such as oxygen or phosphorus, electronic crystal defects (e.g., that may be induced by power laser crystallization), gate oxide thickness/interface defects, channel doping, and/or gate-to-channel work function differences. Although the contribution from each factor varies with process parameters within a targeted integration scheme, it is desired to have control over centering the threshold voltage (Vt) of n-type and p-type thin film transistors (TFTs). This is usually achieved by altering the level of channel dopant in the active silicon layer.
In a traditional integration scheme, the Vt shift can be achieved by ion implantation of n-type or p-type dopant. This shifts the Vt to more negative or positive values, respectively. Ion implantation may be performed as a blanket process or a masked process, but nevertheless involves the addition of multiple extra steps and capital equipment, an increase in cycle time, and/or an introduction of defects and/or yield losses into the process flow.